Driftcorrection for LC-oscillators

"Huff and puff" stabiliser.

T here has been written a lot about stabilising VFO's since the late Klaas Spaargaren, PAoKSB published his first article on this subject some 25 years ago. Over the years, many amateurs have copied PAoKSB's method and in December 1996 Klaas published an improved version in the Dutch amateur radio magazine "Electron".
At that moment I was trying to minimise the drift of the VFO (5-5,5MHz) in my homemade QRP RTx.

Unfortunately there was no print design available so I made one which is described here. At the end of this page you can find a download link for the schematic, layout plans and a HPGL file for printing your own 1:1 pcb. In short terms I'll explain how the circuit works. Keep in mind, that the circuit itself is not my design, but from Klaas Spaargaren PAoKSB who originated the system in the 1970's.

Why an improved design. Does the old one malfunction? No, but the counter method used in the first design was to slow and due too modern IC's an improvement was possible.

Block diagram

Klaas used a D-flipflop as a digital mixer to downconvert the VFO frequency and a crystal reference signal to a much lower value for further treatment. This signal is than compared with another low value signal and when the VFO drifts away it is regulated to its original frequency by means of a varicap in the VFO until both values are equal again. This method has a significantly better performance than the counter method.

Schematic Click to see a full screen color picture of the schematic or component layout. Component layout

Shown is a practical circuit for the improved system. Two cascaded binary dividers, U1 and U2 divide the VFO frequency by 32768 in 15 cascaded stages. This forms the clock signal for the 74HC74 D-flipflop. The crystal oscillator operates at 48MHz using a 16MHz crystal. Q1 and Q2 (S1 and S2 in the block schematic) are both normally off with an on time determined by the differentiating RC networks in their bases and is less than 1mS per pulse. The output voltage has a range of 0 to 10V. After turn-on it starts in the middle of its range. To reset the circuit press S3 (panel mounted). The varicap tuning must be approximately 1kHZ/Volt.



(52 x 67mm)


Testing the dividers:
- the amplitude of the VFO signal to the first divider must be about 4V p-p
- the amplitude of the crystal oscillator must be 4V too (point T) measured with a
  multimeter and adjusted by the trimmer. Precise frequency is unimportant.
- pins 14 and 15 of U2 are LF signals (152Hz and 38Hz when the VFO is 5MHz). 
  The output will be square waves and a DC voltmeter should indicate 2,5V. When not
  working, the output will be either 0 or 5V. You can also check with an earphone and
  series resistor for sharp sounding ticks.

Testing the integrator U4:
- temporarily loosen the 4M7 resistors
- push S3 for reset
- point V should measure about 5V DC
- connect point A several seconds to 0V. The 10M resistor will load the 2,2uF
- point V should increase 1V every 4,4 second
- release point A to check the level at point V . It should not change anymore.

Testing the comparison circuit Q1 and Q2:
- again loosen the 4M7 resistor from Q1
- only Q2 is active now and the DC voltage at point V should decrease 1V per 100 sec.
- resolder the 4M7 resistor.

Last check:
Slowly move your hand towards the VFO when tuned at a calibration signal. You should hear the stabiliser correcting the VFO signal.




Download Schematic, Component layout, Bill of materials and PCB Files  (130Kb)

- VERON's magazine Electron (December 1996, p517-521 and January 1997, p10)
- RadCom's Technical Topics (July; August, p80 and September 1996, p68)
- The ARRL's QEX (February 1996, p19-23)
- RSGB Handbook 1994